It is well known that integrated circuits can suffer from a variety of failure mechanisms, some of which occur in process or under use conditions. Today's integrated circuits are both vertically and horizontally integrated and can incorporate multiple levels of metallization. Dimensional size of structure has dropped to 0.65 .mu. with 0.5 .mu. to 0.35 .mu. scaling anticipated shortly. The increased miniaturization has led to higher chip clock rates with speeds of 66 to 100 MHz fully achievable. To permit defect-free production, failure mechanisms must be precisely located within the complex three-dimensional structure of the circuit. Locating defects requires two types of instruments: sophisticated imaging systems and test equipment capable of exercising the circuit under normal clock operating rates.
U.S. Pat. No. 4,811,090 and earlier related U.S. Pat. Nos. 4,755,874 and 4,680,635 disclosed an image emission microscope which localizes defects in integrated circuits. The emission microscope is based on the principal of recombinant radiation. In an excess current drawing condition such as occurs during failure, electrons and holes in silicon recombine and relax, giving off a photon of light which is readily detected by specialized intensified CCD sensors (night vision equipment). Semiconductor manufacturers typically perform this technique on wafers and on delidded or decapsulated finished devices. The technique is utilized to locate the exact location of defects both on the chip face and from beneath overlying metalization, thereby permitting location of defects within the three-dimensional environment of the circuit. Spatial resolution is 0.5 .mu.. The technique provides evidence of defects such as latchup initiation sites, forward and reverse biasing of junctions, leakage, hot electron and dielectric related defects.
Prior art for biasing of the chip during such testing has generally consisted of two-channel DC power supplies or curve tracers, which provide basic power requirements to the chip. This method has not proven adequate for testing logic devices such as microprocessors and ASICs (Application Specific Integrated Circuits), and all memory devices. These devices require that the chip be exercized to perform certain functions before function related defects can be detected.
This parametric and software chip conditioning is performed by ATE (Automatic Test and Evaluation) production testers which combine precise chip level biasing with software capable of exercising the circuit. ATE equipment can send these test parameters (vectors) to the chip at functional real time clock rates. Many failures are detectable only when functionally evaluated at full chip overating speeds, and then only after an entire series of preceding vectors have been implemented.
ATE software is custom and device-specific. Defects which are detected while operating at full clock speed on these systems are routinely forwarded to failure analysis groups in order to localize the defects. The only current method for linking ATE equipment and an Emission Microscope is by remote cables. The device under test (DUT) is decapsulated or delidded to expose the die surface for emission inspection. The DUT is secured in a socket, placed on the stage of the Emission Microscope which in turn is completely enclosed in a light tight housing. Cables bring the test vectors from the ATE test head to the socket and the DUT. The distance between the ATE tester which is situated outside the light tight enclosure and the DUT is often greater than 6 to 10 feet. The transmission delay resulting from this length of electrical cable greatly limits the ATE signal repetition rate.
Alternately, many failure analysis groups utilize a less sophisticated tester. These testers attempt to simulate the software of the larger production tester, but do so by using different software, which performs a translation of the production tester software, and which performs algorithmic approximations of transmission delays caused by the cabling. The combination of essentially different software and conduction timing delays can make failure conditions both undetectable and non-reproducible. As a result, certain functional failures can never be completely analyzed.
The present invention is directed to a transportable emission microscope that can move freely on the test floor and which is capable of "garaging" the entire ATE test head and docking it in a light-tight manner directly to the stage of an emission microscope. In this way, the DUT is secured to the ATE test head just as it is when it is to be tested independently. By looping suspect test vectors repetitively in order to strobe the light emitted by the failure mechanism with a triggered emission sensor, an emission image can be generated which shows the failure sites. This provides for a significant reduction in the time required to localize the defect for failure analysis.
The docking emission microscope (DEMI) of the invention addresses the following problems:
1. It utilizes existing ATE tester software, the same software used to reveal the parametric failure.
2. The transportable emission microscope "garages" the ATE test head in a light-tight manner for docking to the emission microscope, bringing the DUT directly within the focal plane of the Emission Microscope objectives.
3. Once garaged and docked the chip can be exercised at actual clock speeds thereby reducing any uncertainty in the failure analysis. It eliminates the need, expense and unpredictability of custom cable sets.
4. A triggered camera is tied to the ATE tester and is controlled by ATE software to trigger the camera to turn on at the exact moment for emission detection. This provides for resolution of both static/fixed and dynamic/transient events that occur on these types of devices. By dynamically moving this window forward or backward over the list of test vectors it is possible to confirm the significance of a particular variable and its relationship to producing the emission being imaged.